Signal Integrity Engineer Intern

Job description

Signal Integrity Engineer Intern Location: San Jose, California, United States About the role Astera Labs is seeking a Signal Integrity Engineer Intern to join the Signal and Power Integrity (SI/PI) team. In this role, you will gain hands-on experience analyzing high-speed interconnects and supporting PCB- and system-level designs through simulation, measurement, and cross-functional engineering collaboration. You will work on a meaningful project with guidance from experienced engineers while building practical skills in signal-integrity analysis, lab validation, technical communication, and engineering judgment. What you will do Support pre-layout, layout, and post-layout signal-integrity analysis for high-speed PCB and system designs. Build or update simulation models and analyze critical interconnect behavior, including impedance, insertion loss, return loss, reflections, and crosstalk. Assist with S-parameter extraction, simulation, measurement, and interpretation for high-speed channels and differential signals. Support lab validation using equipment such as time-domain reflectometers, vector network analyzers, high-speed oscilloscopes, spectrum analyzers, and probing fixtures, with appropriate mentorship. Help plan and execute PCB/PCBA validation activities, prioritize critical items, and document results. Organize raw measurement data, screenshots, S-parameter files, and analysis results in project documentation. Collaborate with electrical, layout, validation, NPI, and other engineering partners to investigate issues and communicate findings. Contribute to technical reports, design reviews, and a final project presentation that explains the work, results, and impact. What you bring Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, or a related field. Academic, research, or project experience with one or more of the following: high-speed digital design, signal integrity, transmission lines, electromagnetics, PCB design, differential signaling, or S-parameters. A foundational understanding of frequency-domain or time-domain analysis and how interconnect design affects signal quality. Ability to learn simulation and measurement workflows, work carefully with technical data, and communicate conclusions clearly. Strong ownership, curiosity, practical judgment, and willingness to collaborate across functions. Preferred qualifications Familiarity with PCB or system-level SI/PI simulation, channel analysis, or lab measurement. Exposure to tools or workflows used for high-speed analysis, such as ADS, HFSS, CST, Keysight, Cadence, or equivalent platforms. Experience with Python, MATLAB, or another scripting language for data processing and engineering analysis. Familiarity with calibration, de-embedding, Touchstone/S-parameter files, eye diagrams, or BER analysis. Internship experience and compensation This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges from $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns participate in Early Career programming, including technical and professional-development sessions, community events, and an end-of-program project presentation. Equal opportunity Astera Labs is an equal opportunity employer committed to fostering a diverse and inclusive workplace. We encourage anyone with relevant experience to apply.